1. Field of the Invention
The present invention is related to integrated circuit (IC) chips and more particularly, to IC chips with CMOS SRAM cells and logic.
2. Background Description
Integrated circuit (IC) chip developers' primary goals are faster, denser, lower power IC chips. Typical, state of the art IC chips are manufactured, currently, in the complementary insulated gate Field Effect Transistor (FET) technology, commonly referred to as CMOS. Normally, each generation of CMOS technology is identified by its minimum feature size, e.g. {character pullout}half micron CMOS{character pullout} or {character pullout}quarter micron CMOS{character pullout}. Reducing the minimum feature size is the usual approach to making CMOS chips faster and denser simultaneously with reducing power.
Since the active area (channel region) of any given circuit amounts to less than 10% of the entire area of the circuit, designers are acutely aware that, no matter how small a circuit is, circuit area may still be reduced. However, reducing feature size alone may lead to problems that require other, non-geometric solutions, such as enhanced circuit wiring layers. Even using these state of the art non-geometric enhancements, circuit area reduction falls far short of 90%.
Reducing inactive area in an individual logic gate might have an insignificant impact on overall chip density. By contrast, reducing cell size in a Random Access Memory (RAM) array translates to a corresponding chip density improvement.
However, benefits from reducing RAM cell area are often offset by increased radiation sensitivity. Even Static RAM (SRAM) cells become sensitive at some point to alpha particle or cosmic ray radiation. While these effects are exacerbated by reduced SRAM operating voltages, they may be offset by adding selected process features, such as selective cell node capacitance enhancement and increased cell wiring resistance. Unfortunately, these additional features increase SRAM cell size and write time.
Consequently, designers have resorted to other approaches to reducing cell and circuit area, such as vertical devices, e.g., U.S. Pat. No. 5,414,289 to Fitch et al. entitled {character pullout}Dynamic Memory Device Having a Vertical Transistor{character pullout}.
Fitch et al. teaches opening a hole through a conductor layer (the gate) that is sandwiched by two dielectric layers. A thin dielectric layer (gate oxide) is grown on the sides of the gate conductor layer in the hole. This gate oxide layer is a rough indicator of when channel growth should begin and when it should end. Consequently, Fitch et al.'s vertical FETs have substantial gate-drain and gate-source overlap with its associated overlap capacitance, which may be undesirable. This overlap capacitance is part of circuit load capacitance and contributes to other performance problems, such as Miller Effects.
CMOS circuit power is largely a function of supply voltage (V.sub.h), circuit load capacitance (C.sub.L) and operating frequency (i.e., chip clock frequency f.sub.clk). The general CMOS circuit power (P) formula is P=C.sub.L V.sub.h.sup.2 f.sub.clk. Thus, improving performance (increasing f.sub.clk) and reducing power, requires reducing either C.sub.L or V.sub.h or both.
Although, with each feature size reduction, usually, there has been a corresponding reduction in V.sub.h, this has not been the case with C.sub.L. Furthermore, as feature size shrinks, wiring resistance (i.e., per unit line resistance) increases, increasing RC propagation delays, which offsets some performance gains.
Thus, there is a need for CMOS technologies with reduced power supply voltage levels, reduced parasitic capacitance and wiring per unit length resistance, as well as reduced critical CMOS device parameters, such as channel length.